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| PMV40UN trenchmos? ultra low level fet rev. 01 05 august 2003 product data 1. product pro?le 1.1 description n-channel enhancement mode ?eld-effect transistor in a plastic package using trenchmos? technology. product availability: PMV40UN in sot23. 1.2 features 1.3 applications 1.4 quick reference data 2. pinning information n ultra low level threshold n surface mount package. n battery management n high-speed switch. n v ds 30 v n i d 4.9 a n p tot 1.9 w n r dson 47 m w . table 1: pinning - sot23, simpli?ed outline and symbol pin description simpli?ed outline symbol 1 gate (g) sot23 2 source (s) 3 drain (d) msb003 top view 12 3 s d g mbb076 product specification sales@twtysemi.com 1 of 3 http://www.twtysemi.com
PMV40UN trenchmos? ultra low level fet 3. ordering information 4. limiting values table 2: ordering information type number package name description version PMV40UN - plastic surface mounted package; 3 leads sot23 table 3: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage (dc) 25 c t j 150 c - 30 v v dgr drain-gate voltage (dc) 25 c t j 150 c; r gs =20k w -30v v gs gate-source voltage (dc) - 8v i d drain current (dc) t sp =25 c; v gs = 4.5 v; figure 2 and 3 - 4.9 a t sp = 100 c; v gs = 4.5 v; figure 2 - 3.1 a i dm peak drain current t sp =25 c; pulsed; t p 10 m s; figure 3 - 19.6 a p tot total power dissipation t sp =25 c; figure 1 - 1.9 w t stg storage temperature - 55 +150 c t j junction temperature - 55 +150 c source-drain diode i s source (diode forward) current (dc) t sp =25 c - 1.6 a i sm peak source (diode forward) current t sp =25 c; pulsed; t p 10 m s - 6.4 a product specification sales@twtysemi.com 2 of 3 http://www.twtysemi.com PMV40UN trenchmos? ultra low level fet 5. characteristics table 4: characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit static characteristics v (br)dss drain-source breakdown voltage i d = 250 m a; v gs =0v t j =25 c 30--v t j = - 55 c 27--v v gs(th) gate-source threshold voltage i d = 1 ma; v ds =v gs ; figure 9 v t j =25 c 0.45 0.7 - v t j = 150 c 0.25 0.4 - v i dss drain-source leakage current v ds =30v; v gs =0v t j =25 c --1 m a t j = 150 c - - 100 m a i gss gate-source leakage current v gs = 8 v; v ds = 0 v - 10 100 na r dson drain-source on-state resistance v gs = 4.5 v; i d =2a; figure 7 and 8 t j =25 c - 40 47 m w t j = 150 c - 68 79.9 m w v gs = 2.5 v; i d = 1.5 a; figure 7 and 8 - 4553m w v gs = 1.8 v; i d =1a; figure 7 and 8 - 5573m w dynamic characteristics q g(tot) total gate charge i d = 1 a; v dd =15v; v gs = 4.5 v; figure 13 - 9.3 - nc q gs gate-source charge - 0.7 - nc q gd gate-drain (miller) charge - 2.2 - nc c iss input capacitance v gs =0v; v ds = 30 v; f = 1 mhz; figure 11 - 445 - pf c oss output capacitance - 65 - pf c rss reverse transfer capacitance - 50 - pf t d(on) turn-on delay time v dd =15v; r l =15 w ; v gs = 4.5 v; r g =6 w -6-ns t r rise time -12-ns t d(off) turn-off delay time - 38 - ns t f fall time -12-ns source-drain diode v sd source-drain (diode forward) voltage i s = 1.25 a; v gs =0v; figure 12 - 0.66 1.2 v product specification sales@twtysemi.com 3 of 3 http://www.twtysemi.com |
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